1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a field effect semiconductor integrated circuit device having a via hole in an epitaxial layer in which leakage current from the epitaxial layer to the via hole is positively prevented, as well as to a method of manufacturing such a device.
2. Description of the Related Art
In power amplifiers dealing with high-frequency signals such as high power amplifiers, amplifiers provided at antenna portions of satellite communications equipment, pocket telephones and the like, there have been employed field effect transistors using compound semiconductors capable of providing high power and high speed response.
FIG. 26 illustrates a typical example of such a semiconductor device which is known to the applicant. In this figure, a semiconductor device 1 comprises a semiconductor element 2 in the form of a field effect transistor 2, a compound semiconductor substrate 3 formed of a compound material having a semi-insulating property such as gallium arsenide (GaAs), indium phosphide (InP), etc., a p-type buffer layer 4 formed on the substrate 3, an n-type semiconductor layer 5 formed on the p-type buffer layer 4, and a semiconductor element forming region 6 provided in the n-type semiconductor layer 5, the region 6 acting as an active layer of the field effect transistor. The active layer 6 is formed with a recess 7 in which a gate electrode 8 is provided. A drain electrode 9 and a source electrode 10 are provided on the n-type semiconductor layer 5 on the opposite sides of the gate electrode 8.
In the n-type semiconductor layer 5 there is provided an isolation region 11 which is formed by an ion implantation using an ion source formed, for example, of boron, for the purpose of dividing the area of the active layer 6.
A via hole 12 passes through the substrate 3, the buffer layer 4 and the semiconductor layer 5 so that a backside electrode 13 on the surface of the substrate 3 is electrically connected to a via hole upper electrode 14 in the form of a wiring layer formed on the surface of the semiconductor device 1, the via hole upper electrode 14 being further electrically connected to the source electrode 10.
The semiconductor device 1 is substantially constructed as follows.
The p-type buffer layer 4 and the semiconductor layer 5 are deposited in succession on the substrate 3 and boron ions are implanted or doped into the thus deposited layers while leaving the active layer 6 intact to thereby make the n-type semiconductor layer 5 non-conducive, thus performing regional division between the active layer 6 in the form of a semiconductor element forming region and the isolation region 11.
Subsequently, the drain electrode 9 and the source electrode 10 are formed on the active layer 6 by means of a vapor-deposition and lift-off method, and then the recess 7 is formed by etching and the gate electrode 8 is provided by the vapor-deposition and lift-off method while adjusting a current supplied thereto.
The via hole upper electrode 14 is provided by the vapor-deposition and lift-off method in such a manner that it is electrically connected to the source electrode 10. Thereafter, the via hole 12 is formed through the deposited layers from the substrate side by, for example, sulfuric acid etching, and then the backside electrode 13 is formed by means of, for example, an electrolytic plating method.
In this type of semiconductor device used with a high power amplifier, power amplification is carried out by maintaining the gate voltage at a constant value ranging from 0 V to -1.5 V with the source electrode 10 being connected to ground through the backside electrode 13 and by changing the voltage of the drain electrode 9 between zero volts and a voltage in the range of 3-10 V.
With the conventional semiconductor device as constructed above, boron ions are implanted or doped into the n-type semiconductor 5 to make it nonconductive. In this case, however, in order to perform ion implantation or through acceleration of an element having a large atomic weight such as boron so as to make a regional division between the active layer 6 of the semiconductor element and the isolation region 11, a high power accelerator is required and it is rather difficult to perform ion implantation or doping to a required depth for providing electrical insulation.
In this type of semiconductor device 1, a depth from the surface of the n-type semiconductor layer 5 through the p-type buffer layer 4 is about 2,000 angstroms to 10,000 angstroms so there is the possibility that the p-type buffer layer can not be rendered insulating to a satisfactory extent by means of the ion implantation or doping of boron.
In cases where the p-type buffer layer 4 in the lower portion of the isolation region 11 is not rendered insulating to any satisfactory extent, the gate electrode 8 of the field effect transistor 2 is supplied with a negative voltage, the absolute value of which is less than a pinch-off voltage therefor, so that a forward direction current flows between the depleted active layer 6 and the p-type buffer layer 4, and further from the buffer layer 4 to the source electrode 10 through the backside electrode 11 and the via hole upper electrode 13. Thus, there develops a leakage current between the gate electrode 8 and the source electrode 10, posing the problem that the gate-source dielectric resistance is reduced.
An example of coping with such a problem of leakage current occurring in the inner surface of a via hole is described in Patent Laid-Open No 4-39968. In this example, essential portions of the inner surface of the via hole are doped with ions such as protons, oxygen, etc., to partially isolate the via hole inner surface to thereby provide an isolation layer havingof a thickness in the range of from about 2 micrometers to about 50 micrometers. Thereafter, a via hole wiring layer is formed on the isolation layer whereby a source electrode and a backside electrode are connected to each other, thus preventing leakage current through a buffer layer.
In this case, the active layer, the buffer layer and the substrate, through which the via hole is to be formed, are subjected to ion implantation or doping to first provide the isolation layer or semi-insulating region, and thereafter the via hole is subsequently formed through the layers while leaving the isolation region.
Here, it is to be noted that if protons are used with this method, electrical properties of a field effect transistor, a heterojunction bipolar transistor (HBT) and the like having a high mobility transistor (HEMT) type structure may be adversely be affected by protons. Therefore, it is rather difficult to employ this method in general as a versatile technology.
Another example is disclosed in Patent Laid-Open No. 3-153057 in which an insulating film such as a silicon nitride film, a silicon oxide film and the like is formed on the inner surface of a via hole by means of a chemical vapor deposition (CVD) method, a via hole wiring layer is then formed on the insulating film to thereby provide electrical connection between a source electrode and a backside electrode. In this manner, leakage current through a buffer layer is prevented.
In this case, however, an etching process is required in which formation of a master pattern and etching are performed for removing the insulating film which is disposed on the backside surface of the source electrode and directed toward the inside of the via hole prior to the processes in which the via hole is formed through the deposited layers from the side of the semiconductor substrate, with the insulating film being then formed on the inner surface of the via hole and the via hole wiring layer being formed thereon to provide electrical connection between the source electrode and the backside electrode.